1. Field of the Invention
The invention relates to a method of planarization, and more particularly, to a method of spin-on-glass (SOG) planarization.
2. Description of the Related Art
To fabricate metal interconnects on a wafer with a limited surface area, and to meet the requirement of the booming technology of integrated circuit, more than one metal layers are required to achieve a multilevel interconnection. The metal layers are isolated by dielectric material to avoid a short circuit. However, an uneven surface profile of the integrated circuit is typically formed due to the formation of the metal layers. The uneven surface profile causes the formation of voids in the subsequently formed dielectric layer. In addition, it is difficult to form another metal layer on a dielectric layer with an uneven surface. Therefore, a planarization process is typically performed on the dielectric layer.
Spin-on-glass is a widely applied planarization method in semiconductor. A solvent containing dielectric material is evenly spin coated on a wafer. The dielectric material is carried by the solvent which flows on the surface of the wafer. The dielectric material is thus easily filled into gaps or trenches of an uneven surface of the wafer. Using a thermal treatment, the solvent is removed to cure the spin-on glass. The planarization is thus achieved. The gap filling property of spin-on-glass technique is often applied to solve the problems of the formation of voids within a dielectric layer.
FIG. 1A to FIG. 1C shows a conventional spin-on-glass process for forming a sandwich type dielectric layer. In FIG. 1A, conductive wires 102a, 102b and 102c are formed on a substrate 100. A conformal dielectric layer 104 is to cover the substrate 100 and the conductive wires 102a to 102c. Two to three times of spin coating are performed on the dielectric layer 104. After a curing process, a spin-on-glass layer 106 is formed on the dielectric layer 104. The SOG layer 106 is apparently thicker over the conductive wire 102a which has a larger surface area.
In FIG. 1B, an etch back process is performed on the SOG layer 106. The SOG layer 106 over the conductive wires 102a to 102c is removed until the underlying dielectric layer 104 is exposed. The resultant SOG layer is then denoted as 106a.
In FIG. 1C, a dielectric layer 108 is formed to cover the dielectric layer 104 over the conductive wires 102a to 102c and the SOG layer 106a.
Due to the absorption of SOG material, the SOG layer 106 (FIG. 1A) over the conductive wires 102a to 102c have to be removed to prevent a subsequently formed contact window being poisoned by the evaporated of water or moisture absorbed by the SOG layer. As mentioned above, the SOG layer 106 is thicker over a larger surface such as the conductive wire 102a. To remove the thicker part of the SOG layer 106 over the larger surface, recessed or hollow surface is formed in other parts of the SOG layer as shown in FIG. 1B. The planarization is thus affected.
To improve the level of planarity, FIG. 2A to FIG. 2B shows another conventional method ot planarization. In FIG. 2A, conductive wires 202a, 202b, and 202c are formed on a substrate. A conformal dielectric layer 204 is formed to cover the conductive wires 202a to 202c and the substrate 200. Two to three times of spin-on-glass coating are performed on the dielectric layer 204. After a curing process, a SOG layer 206 is formed on the dielectric layer 204. A dielectric layer 208 and a photo-resist layer 210 is formed on the SOG layer 206.
In FIG. 2B, an etch back process is performed to planarize the photo-resist layer 210 and the dielectric layer 208. The photo-resist layer 210 is stripped, and a part of the dielectric layer 208 is removed until the dielectric layer 204 over the conductive wires 202a to 202c is exposed. The remaining dielectric layer is denoted as 208a.
By the above method, the level of planarity is enhanced. However, as the thickness to be etched back is large, so that a long etching back time is consumed. To perform the etching back process with a long time often causes a thicker part in the central of the wafer, and a thinner part on the edge. Defects thus easily occur on the edge of a wafer. In addition, the SOG layer is partly remained over the conductive wires, so that a contact window formed subsequently is very likely to be poisoned.